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Group Meeting

Synthesis & Verification

  • 2009-11-09

  • On the Decreasing Significance of Large Standard Cells in Technology Mapping

  • 2010-04-30

  • Simulation and SAT-Based Boolean Matching for Large Boolean Networks

Escape Routing & Chip-Package Co-design

  • 2008-01-09

  • Optimal Bus Sequencing for Escape Routing in Dense PCBs

  • 2008-01-16

  • Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards

  • 2008-05-29

  • Ordered Escape Routing Based on Boolean Satisfiability

  • 2008-07-31

  • EFFICIENT ESCAPE ROUTING FOR HEXAGONAL ARRAY OF HIGH DENSITY IOS

  • 2008-09-11

  • Routability Driven Modification Method of Monotonic Via Assignment for 2-layer Ball Grid Array Packages

  • 2008-12-12

  • AREA-I/O FLIP-CHIP ROUTING FOR CHIP-PACKAGE CO-DESIGN

  • 2009-03-06

  • IO CONNECTION ASSIGNMENT AND RDL ROUTING FOR FLIP-CHIP DESIGNS

  • 2009-04-02

  • On Using SAT to Ordered Escape Problems

  • 2009-09-10

  • Automatic Bus Planner for Dense PCBs

  • 2009-09-18

  • A Correct Network Flow Model for Escape Routing

  • 2010-01-27

  • Optimal Simultaneous Pin Assignment And Escape Routing For Dense PCBs

  • 2010-04-16

  • B-Escape: A Simultaneous Escape Routing Algorithm Based on Boundary Routing

  • 2010-07-16

  • A Negotiated Congestion based Router for Simultaneous Escape Routing

  • 2010-11-29

  • On the Escape Routing of Differential Pairs

Floorplan & Placement

  • 2007-07-31

  • Improving Voltage Assignment byOutlier Detection and Incremental Placement

  • 2007-09-04

  • A Transitive-Closure-Graph-Based Macro Placement Algorithm

  • 2007-11-21

  • Temperature Aware Microprocessor Floorplanning Considering Application Dependent Power Load

  • 2008-01-02

  • Voltage Island-Driven Floorplanning

  • 2008-09-26

  • Bus-Driven Floorplanning

  • 2008-11-28

  • Corner Block List Representation and Its Application to Floorplan Optimization

  • 2008-12-05

  • Deferred Decision Making Enabled Fixed-Outline Floorplanner

  • 2008-12-26

  • An Integrated Nonlinear Placement Framework withCongestion and Porosity Aware Buffer Planning

  • 2008-12-31

  • Constraint Graph-Based Macro Placement for Modern Mixed-Size Circuit Designs

  • 2009-03-27

  • Exploring Adjacency in Floorplanning

  • 2009-04-10

  • A Revisit to Floorplan Optimization by Lagrangian Relaxation

  • 2009-04-17

  • Linear Constraint Graph for Floorplan Optimization with Soft Blocks

  • 2009-07-10

  • Multi-Voltage Floorplan Designwith Optimal Voltage Assignment

  • 2009-07-24

  • Modern floorplanning with boundary clustering constraint

  • 2009-08-14

  • Effective Wire Models for X-Architecture Placement

  • 2009-08-21

  • Spare-Cell-Aware Multilevel Analytical Placement

  • 2009-08-27

  • Register Placement for High-Performance Circuits

  • 2009-09-04

  • Handling Complexities in Modern Large-Scale Mixed-Size Placement

  • 2009-09-25

  • Guiding Global Placement with Wire Density

  • 2010-02-11

  • Configurable Multi-product Floorplanning

  • 2010-06-18

  • A Novel Fixed-outline Floorplanner with Zero Deadspace for Hierarchical Design

  • 2010-07-23

  • History-based VLSI Legalization using Network Flow

  • 2010-08-20

  • Fixed Outline Multi-Bend Bus Driven Floorplanning

  • 2010-09-20

  • Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization

  • 2010-10-25

  • Bus-Pin-Aware Bus-Driven Floorplanning

  • 2010-11-08

  • GRPlacer: Improving Routability and Wire-Length of Global Routing with Circuit Replacement

  • 2011-01-10

  • Performance-driven Analog Placement Considering Boundary Constraint

  • 2011-02-22

  • Pulsed-Latch Aware Placement for Timing-Integrity Optimization

Routing

  • 2007-10-03

  • A Network-Flow Based Algorithm for Digital Microfluidic Biochip Routing

  • 2007-11-28

  • Novel Wire Density Driven Full-Chip Routing for CMP Variation Control

  • 2007-12-05

  • Efficient Multi-Layer Obstacle-Avoiding Rectilinear Steiner Tree Construction

  • 2008-02-21

  • An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design

  • 2008-03-20

  • ARCHER:A HISTORY-DRIVEN GLOBAL ROUTING ALGORITHM

  • 2008-03-27

  • BoxRouter 2.0: Architecture and Implementation of a Hybrid and Robust Global Router

  • 2008-05-15

  • Trunk Decomposition BasedGlobal Routing Optimization

  • 2008-06-12

  • MAIZEROUTER: Engineering an Effective Global Router

  • 2008-06-26

  • SidewinderA Scalable ILP-Based Router

  • 2008-07-10

  • A New Global Router for Modern Designs

  • 2008-08-14

  • FAST GLOBAL ROUTING WITH FORBIDDEN-REGION REROUTING

  • 2008-09-19

  • AN EFFICIENT ALGORITHM FOR OBSTACLE-AVOIDING RECTILINEAR STEINER TREE CONSTRUCTION

  • 2009-01-09

  • BSG-Route: A Length-Matching Router for General Topology

  • 2009-02-11

  • Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs

  • 2009-02-18

  • UNIFICATION OF OBSTACLE-AVOIDING RECTILINEAR STEINER TREE CONSTRUCTION

  • 2009-05-01

  • MULTI-LAYER GLOBAL ROUTING CONSIDERING VIA AND WIRE CAPACITIES

  • 2009-06-12

  • Initial Global Routing in Floorplanning by EQ-Sequence

  • 2009-06-19

  • Fast Route 4.0 �V Global Router with E?cient Via Minimization

  • 2009-07-02

  • Critical-Trunk Based Obstacle-Avoiding Rectilinear Steiner Tree Routings for Delay and Slack Optimization

  • 2009-10-02

  • An O(n log n) Path-Based Obstacle-Avoiding Algorithm for Rectilinear Steiner Tree Construction

  • 2009-12-04

  • ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips

  • 2010-03-12

  • Obstacle-avoiding Rectilinear Steiner Tree Construction

  • 2010-03-30

  • Obstacle-Aware Longest Path using Rectangular Pattern Detouring in Routing Grids

  • 2010-06-11

  • CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles

  • 2010-07-30

  • Multi-Threaded Collision-Aware Global Routing with Bounded-Length Maze Routing

  • 2010-09-03

  • A Parallel Integer Programming Approach to Global Routing

  • 2010-09-27

  • Obstacle-Avoiding Rectilinear Steiner Tree Construction Based On Steiner Point Selection

DFM

  • 2009-06-03

  • Layout Decomposition for Double Patterning Lithography

  • 2009-06-26

  • Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

  • 2009-07-17

  • Double Patterning TechnologyFriendly Detailed Routing

  • 2009-11-20

  • GREMA: Graph Reduction Based Efficient MaskAssignment for Double Patterning Technology

  • 2009-12-18

  • Simultaneous Layout Migration and Decompositionfor Double Patterning Technology

  • 2010-03-05

  • On Process-Aware 1-D Standard Cell Design

  • 2010-12-06

  • Native-Conflict-Aware Wire Perturbation for Double Patterning Technology

  • 2011-03-08

  • Mask Cost Reduction with Circuit Performance Consideration for Self-Aligned Double Patterning

Power

  • 2008-01-23

  • An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning

  • 2010-03-26

  • Simultaneous Control of Power/Ground Current, Wakeup Time andTransistor Overhead in Power Gated Circuits

  • 2010-05-14

  • Low Power Gated Bus Synthesis using Shortest-Path Steiner Graph for System-on-Chip Communications

  • 2010-07-02

  • Simultaneous Clock Buffer Sizing and Polarity Assignmentfor Power/Ground Noise Minimization

  • 2010-08-06

  • Synthesis and Implementation of Active Mode Power Gating Circuits

  • 2010-10-11

  • Clock Buffer Polarity Assignment Considering Capacitive Load

  • 2010-12-27

  • The Fast Optimal Voltage Partitioning Algorithm For PeakPower Density Minimization

Clock Network

  • 2007-10-31

  • Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building

  • 2010-06-26

  • Accurate Clock Mesh Sizing via Sequential Quadratic Programming

  • 2010-09-10

  • Fast Timing-Model Independent Buffered Clock-Tree Synthesis

  • 2011-02-14

  • Low-power Clock Trees for CPUs

FPGA

  • 2007-11-14

  • Timing-Driven Placement for Heterogeneous FPGA

  • 2008-08-21

  • ON THE INTERACTION BETWEEN POWER-AWARE

Buffer insertion & ECO

  • 2008-05-08

  • Path Based Buffer Insertion

  • 2008-06-19

  • ECO Timing Optimization Using Spare Cells

  • 2008-07-24

  • Reap What You Sow: Spare Cells for Post-Silicon Metal Fix

  • 2008-09-04

  • Engineering change using spare cells with constant insertion 

  • 2008-10-03

  • Circuit-wise Buffer Insertion and Gate Sizing Algorithm with Scalability

  • 2009-10-16

  • New Spare Cell Design for IR Drop Minimization in Engineering Change Order

  • 2009-11-06

  • Matching-Based Minimum-Cost Spare Cell Selection for Design Changes

SSTA

  • 2008-04-17

  • Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources

  • 2008-06-05

  • Statistical Gate Delay Model for Multiple Input Switching

  • 2008-07-03

  • NON-PARAMETRIC SSTA:AN SSTA FRAMEWORK FOR ARBITRARY DISTRIBUTION

Thermal Modeling

  • 2008-07-17

  • Stochastic Modeling of a Thermally-Managed Multi-Core system

Pin/Via Assignment

  • 2007-12-19

  • Module Assignment for Pin-Limited Deign under the stacked-Vdd Paradigm

  • 2008-08-28

  • Novel Pin Assignment for Components with Very High Pin Counts

  • 2008-10-31

  • Post-Placement Pin Optimization

  • 2008-11-19

  • Path Smoothing via Discrete Optimization

3D-ICs

  • 2007-12-12

  • Thermal-aware Steiner Routing for 3D Stacked ICs

  • 2008-04-10

  • 3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits

  • 2008-10-17

  • 3-D Floorplanning Using Labeled Tree and Dual Sequences

  • 2008-11-14

  • Thermal-Driven Multilevel Routing for 3-D ICs

  • 2008-12-18

  • A THERMAL-DRIVEN FLOORPLANNING ALGORITHM FOR 3D ICS

  • 2009-02-27

  • Thermal-Aware 3D IC Placement Via Transformation

  • 2009-03-13

  • Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

  • 2009-04-24

  • A Multilevel Analytical Placement for 3D ICs

  • 2009-06-05

  • A Novel Thermal Optimization Flow Using Incremental Floorplanning for 3D ICs

  • 2009-10-23

  • Integrated Interlayer Via Planning and Pin Assignment for 3D ICs

  • 2009-11-12

  • Reliability Aware Through Silicon Via Planning for 3D Stacked ICs

  • 2009-12-11

  • Thermal-Aware Memory Mapping in 3D Designs

  • 2009-12-25

  • Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning

  • 2010-01-08

  • LP Based White Spcae Redistribution for Thermal Via Planning and Performance Optimization in 3D ICs

  • 2010-03-19

  • Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs

  • 2010-04-09

  • An Analytical Placer for Mixed-Size 3D Placement

  • 2010-05-07

  • Pre-bond Testable Low-Power Clock Tree Design for 3D Stacked ICs

  • 2010-10-04

  • Clock tree synthesis with pre-bond testability for 3D stacked IC designs

EDA on GPU

  • 2010-08-27

  • An Effective GPU Implementation of Breadth-First Search

  • 2010-11-01

  • Accelerating Statistical Static Timing Analysis Using Graphics Processing Units

  • 2010-12-20

  • Fast Thermal Analysis on GPU for 3D-ICs with Integrated Microchannel Cooling

Others

  • 2009-07-31

  • Post-Floorplanning Power/Ground Ring Synthesis for Multiple-Supply-Voltage Designs

  • 2010-01-15

  • Scheduling with Soft Constraints

  • 2010-09-17

  • Connected K-Coverage Problem in Sensor Networks

  • 2010-12-13

  • On Timing-Independent False Path Identification

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